Jan 7, 2019 - Jan 9, 2019
Department of Electronics & Communication Engineering of SJEC is organizing Three day Faculty Development Program on “FINFET BASED VLSI DESIGN USING CADENCE” from 7th January to 9th January 2019. The main aim of the FDP is focus on recent trends in Analog VLSI design. The topics are carefully chosen so as to enable the participants particularly the faculty get introduced to Analog front and back end design process. Considering the current trends in VLSI lab and its eminent inclusion with academic as well as student projects, a demo to work with FINFET will also be provided.