Educational Details

Degree : B.E.
Year : 2009
University : V.T.U
PG Degree : M.E.
Year : 2012
University : University of Western Australia

Teaching Experience

i) 07/2013 to 06/2014

Electronics and Communication Engineering

AIET, Mijar

Asst Professor


ii) 07/2014 to present

Electronics and Communication Engineering

SJEC, Mangaluru

Asst Professor

Research Experience

01/2011 to 11/2011 Microelectronics Research Group UWA, Western Australia

Industry Experience

07/2012 to 04/2013
ASIC Design and Verification
Maven Silicon
Verification Engineer

Specialization PG

Microlectronics

Subjects teaching at Under Graduate level

Fundamentals of CMOS VLSI, Microelectronics Circuits

Subjects teaching at Post Graduate level

CMOS VLSI Design, Aanlog IC Design

Technical Interest

VLSI, Analog/Digital IC Design and Verification, ASIC Design, Optoelectronics, Solid state devices, Semiconductor Physics

Papers Presented in National Conference

1. An Effective Approach to Perform Multiplication using Residue Number System  
Authors
Phalguna P S, Keith R Fernandes

Publication date
2015/8/13

Conference
National Conference on Advances in Communication and Signal Processing

2.  Comparison of Iterative and Parallel CORDIC Architecture  
Authors
Nagashree, Keith R Fernandes

Publication date
2015/8/13

Conference
National Conference on Advances in Communication and Signal Processing

3. An Effective Algorithm For Multiplication For
Residual Number System
Authors
Phalguna P S, Keith R Fernandes

Conference: 
National Conference on Advanced Innovation in Engineering and Technology (NCAIET-2015)

Date: 1 April 2015

Papers Presented in International Conference

1. Implementation of Chinese Remainder Theorem and Radix 8 Booth Algorithm to perform Multiplication for Residual Number System using Verilog HDL

Conference: 
International Conference on Engineering, Science, Management and Advances in Research Technologies (ICESMART-2015)

Date: 29 April 2015

Number of academic projects guided

UG : 4
PG : 2

Research Project


Workshop Attend

1. Attended one day workshop on "Fundamentals of Analog Integrated Circuit Design", organised by Dept of ECE, SMVITM, Bantakal, on 17 June 2015.
2. Attended five day workshop on "Cadence VLSI Design Tools", organised by Dept of ECE, SJEC, Mangaluru, during 21 to 25, July 2015.
3. Attended five day workshop on "Evolution of Microelectronics",  organised by Dept of EEE and ECE, CEC, Bantwal, during 2 to 6, December 2015.

Workshops/Seminars organized

1. 6 Day Workshop on Digital System Design and Verification using Verilog
Date: 5 to 11 Jan 2015
Venue : Dept of ECE SJEC

2. 5 day workshop on "Cadence VLSI Design Tools",
Date: 21 to 25, July 2015
Venue: VLSI Lab, SJEC Mangaluru

Workshops/Seminars conducted as Resource Persons

1. 6 Day Workshop on Digital System Design and Verification using Verilog
Date: 5 to 11 Jan 2015
Dept of ECE SJEC

2. Seminar on Introduction to VLSI Design 
Date: 01 Aug 2016
Dept of EEE SJEC

Details of membership in Professional bodies

IEEE
Member 
2008

Administrative Responsibilities

IEEE SJEC Student Branch Conselor