The Department of Electronics & Communication Engineering at St. Joseph Engineering College, in association with CoreEL Technologies, organized a two-day FDP on FPGA Design Flow Using PynqZ2 and Analog IC Design Flow on 22nd and 23rd August 2024. The FDP saw active participation from 18 attendees, including participants from various other colleges,and was expertly led by Mr. Vishnudev R Gowda, Application Engineer at AMD Xilinx & MentorGraphics, Bengaluru.
On Day 1, participants were introduced to the Vivado design flow, and FPGA architecture, and engaged in hands-on RTL design and hardware implementation using PynqZ2 boards.
On Day 2,the focus shifted to embedded system design using Zynq, and analog IC design flow withschematic and layout demonstrations.
The event concluded with a vote of thanks and a memento presentation to the resource person.The FDP was coordinated by Ms. Florence Nishmitha and Ms. Vinitha Pasanha, Assistant Professors, Department of ECE.
