The Prodigi - Student Association of ECE organized a Technical talk on “VLSI Design Technology - Future of Fabless in India” for the IV Year ECE Students on December 16, 2024 from 12.00 PM to 1.00 PM. The Resource person for the session was Mr Ranveer Singh, Head of University Relations, Truechip Solutions, Bengaluru.
Mr Ranveer Singh provided valuable insights into the rapidly evolving VLSI industry. He began the session by emphasizing the importance of ensuring the reliability and efficiency of semiconductor systems. The resource person mentioned that India will need 500,000 VLSI engineers by 2026, driven by an increase in international projects and the growth of fabless companies focusing on design innovation. He also elaborated on the distinction between fab and fabless companies, showcasing the advantages of the latter in driving cost-effective and creative solutions.
The session covered the VLSI design flow, detailing front-end processes such as RTL design and verification, as well as back-end tasks like placement and routing. The resource person also highlighted the importance of HDL-Verilog and SystemVerilog as essential tools for building expertise in VLSI. The talk offered a professional and comprehensive overview of the immense opportunities within the semiconductor industry.
The insights provided by the resource person were well-received by the students, who found the session both informative and inspiring.
The program was coordinated by Dr Dayakshini HOD-ECE Department, Ms Reshma K J and Ms K Aarya Shri, Assistant Professors, Department of Electronics and Communication Engineering.
