Analog IC Design Flow using cadence

The Department of Electronics & Communication Engineering at St. Joseph Engineering College, in association with Entuple Technologies Pvt. Ltd, organized a three-day FDP on Analog IC Design Flow using Cadence from 11-13 December 2024. The FDP was expertly led by Mr. Rakesh B R, Field Application Engineer, Entuple Technologies Pvt. Ltd, Bengaluru.

The primary objectives of the workshop were:

1. To provide a comprehensive understanding of full custom IC design flow, utilizing Cadence tools for MOSFET characterization, schematic capture, symbol creation, testbench development, and functional simulation to effectively design and verify integrated circuits
2. To facilitate the design and validation of integrated circuits through layout creation
3. To provide an understanding of the semi-custom IC design flow, utilizing Cadence tools for functional verification and Physical Implementation using Innovus.

On Day 1, the session was conducted by Mr. Vijay Ganesh P.C, Assistant Professor in the Department of Electronics and Communication Engineering at SJEC. He provided participants with an introduction to fundamental VLSI concepts, establishing a solid foundation for the subsequent sessions of the workshop.

On Day 2, participants were introduced to the Full Custom IC Design flow using Cadence. They engaged in hands-on activities, including creating an inverter schematic and performing functional simulations using Spectre. Additionally, the layout for the CMOS inverter was designed, followed by Physical Verification.

On Day 3, the Semi-Custom IC Design flow was demonstrated using a COUNTER as an example. Participants were guided through performing Functional Verification using Cadence Incisive, followed by RTL Synthesis utilizing the Genus Synthesis Solution. The Physical Implementation was carried out using Cadence Innovus. Furthermore, detailed Timing Analysis and Parasitic Extraction were conducted to evaluate the design's performance and ensure its accuracy.

The event, coordinated by Mr. Vijay Ganesh P. C. and Ms. Vinitha Pasanha, Assistant Professors from the Department of ECE, witnessed enthusiastic participation from 26 faculty members and was highly appreciated by all attendees.