ECE: One-week STTP on "Advanced Digital System Design using FPGA"

 

Department of Electronics & Communication Engineering organized a One-week STTP on "Advanced Digital System Design using FPGA" during 18-23 April, 2022 for the VI Semester ECE Students. The STTP was focused mainly on the following objectives:

  1. To Analyze and Design the basic building blocks of Digital Systems using FPGA.
  2. To Design a Microprocessor using RISC ISA Architecture.

The resource persons for the STTP were Mr Vijay Ganesh P C, Assistant Professor, Dr Rohan Pinto, Associate Professor, Ms Deepthi S R, Assistant Professor, Dr Phalguna P S, Associate Professor, Department of ECE, and Mr Mahesha Y, System Engineer, Life Signals Private Limited

The STTP started on 18th April 2022 at 9:30 a.m. in the DSP Lab. Dr Dayakshini, HOD, Department of ECE cordially welcomed the Resource persons and the Students.

The session started with an introduction to the fundamentals of Digital System Design and FPGA.  Students were assigned a task to write a program for 1 bit adder and implement it in  FPGA. Further, verilog code for the logical unit was written and implemented using the FPGA kit.

On the second day, students were introduced to various modules of a processor. Later, the Arithmetic and Logic Unit was implemented and a detailed explanation on how to draw a State diagram and a flow chart was discussed.

On the third day of the STTP, students merged the ALU and Logic Unit, wrote a testbench code and verified the output using the FPGA kit. Later, they were asked to draw a flowchart for the same.

The Day 4 was about memory design, RAM, ROM and discussed Harward and Von Neumann Architecture. The participants wrote a code and testbench  for ROM and verified the output using simulation.

On Day 5, the participants wrote a code and testbench  for RAM and verified the output using simulation. During this session, students were given a brief idea about the requirements to start their career in core companies.

The Resource Person on Day 6 was Mr Mahesha Y, System Engineer, Life Signals Private Limited. He gave insights on IP based design and introduction to UVM based verification.

A detailed and informative explanation along with hands-on training was given in every session during the STTP. Mr Vijay Ganesh P.C, Assistant Professor, Department of ECE handed over a  token of appreciation to Mr Mahesha Y . Ms Jayalakshmi K. P, Ms Priya Seema Miranda and Ms K Aarya Shri, Assistant Professors, Department of ECE,  St Joseph Engineering College coordinated the STTP.