The Department of Electronics & Communication Engineering, in association with the ISTE SJEC Student Chapter and PRODIGI – the ECE Students’ Association – organized a technical talk on “Exploring Careers and Methodologies in the VLSI Industry” on May 15, 2025, at 10:00 AM in Prerana Hall. The session was for second year Electronics and Communication Engineering students to introduce them to the significance of Verilog HDL and its practical application in the VLSI industry.
The resource persons for the session were from Karmic Design Pvt. Ltd. – Mr Pavan Raj, Senior Layout Design Engineer, Mr Deviprasad Nayak, Design Verification Engineer, and Ms Hitha Shetty, Design Verification Engineer. They provided the students with a comprehensive insight into VLSI design methodologies and shared valuable perspectives on the various career opportunities available in the VLSI industry.
Mr Pavan Raj focused on foundational concepts required to enter the VLSI industry. He also gave insights on how to crack interviews in the VLSI domain and highlighted the various career opportunities available for engineering graduates. Mr Deviprasad Nayak and Ms Hitha Shetty provided in-depth insights into the VLSI Integrated Circuit design flow, emphasizing the stages of design verification. They introduced the students to advanced concepts such as SystemVerilog and the Universal Verification Methodology, explaining their significance in VLSI design projects.
The session was coordinated by Dr Jennifer C Saldanha and Ms Reshma K J, Assistant Professors in the Department of Electronics and Communication Engineering. The student coordinators for the session were Ms Oshin D Fernandes and Ms Frenny C Saldanha, II Year, ECE.
