The Department of Electronics & Communication Engineering at St. Joseph Engineering College, in association with KarMic Design Pvt. Ltd, organized a Five-day FDP on Smart Verification of Digital Systems using Industry Tools from 27–31 July, 2026. The FDP was expertly led by Ms Hitha Shetty, Design Engineer I and Ms Pritika Rout, Design Engineer I, Karmic Design Pvt Ltd, Manipal.
The primary objectives of the workshop were:
- To strengthen the conceptual understanding of faculty members in modern digital verification methodologies using SystemVerilog.
- To provide hands-on training in industry-relevant verification practices and coding techniques.
- To bridge the gap between academic instruction and current industry requirements in semiconductor verification
The first day commenced with a brief inaugural programme, during which the resource persons were introduced and the participants were given an overview of the five-day workshop schedule. The technical sessions introduced the participants to the fundamentals of Digital Verification (DV), covering topics such as Verilog vs. SystemVerilog, data types, tasks, functions, and looping constructs, followed by hands-on coding exercises in the afternoon to reinforce the concepts learned during the theory sessions.
On day 2, participants learned Object-Oriented Programming (OOP) concepts in SystemVerilog, including classes and fork-join processes. Practical coding exercises were conducted to provide hands-on experience with these verification concepts.
The third day focused on the SystemVerilog verification architecture, along with events, mailboxes, and constraint-based randomization. Participants implemented and verified a simple adder through coding exercises during the laboratory session.
On day 4, The simple adder design was analyzed in greater detail, with emphasis on its implementation, verification, and debugging techniques. Participants further explored the adder code through practical sessions to strengthen their understanding of SystemVerilog-based verification.
The final day focused on the design and verification of a Single-Port RAM using SystemVerilog. Participants implemented the RAM module through hands-on coding exercises, after which a valedictory programme was held where the resource persons were felicitated by Dr Dayakshini, HOD, ECE Department with mementos and letters of appreciation, and valuable feedback on the workshop was shared by both the internal and external participants.
The event, coordinated by Ms Florence Nishmitha, Ms Vinitha Pasanha, and Ms Savitha J, Assistant Professors, Department of Electronics and Communication Engineering, witnessed enthusiastic participation from 30 faculty members including internal and external and was highly appreciated by all attendees.
