The Department of Electronics and Communication Engineering of St Joseph Engineering College (SJEC), in association with the IEEE Geoscience and Remote Sensing Society Student Chapter and the IEEE SJEC Student Branch, organized a hands-on workshop. Dr Jennifer Saldanha and Ms Florence Nishmitha of the Dept of ECE coordinated the event. The session was conducted for the IV semester ECE students on April 4, 2025 from 2.00 pm to 4.30 pm for section B students and April 7, 2025 from 9.00 am to 1.00 pm for section A students at the DSP Lab, Room No. 1220. Mr Vijay Ganesh P.C, Assistant Professor in the Department of ECE, served as the resource person for the workshop. The event aimed at enhancing students' knowledge of digital circuit design using Verilog HDL.
This approach ensured that the participants were motivated and fully engaged in the session. During the workshop, students were introduced to the basics of Verilog and its application in digital design. Practical exercises included implementing a full adder and analyzing setup delay, hold delay, and power consumption. Participants also designed an ALU, created a testbench for verification, and integrated components like ALU, memory unit, and LCD display into a functional calculator system. Further, instruction fetch using a memory unit was implemented, and simulations were carried out to study performance and debug errors.
The workshop concluded with participants gaining substantial hands-on experience in Verilog coding for both combinational and sequential circuits. They developed an understanding of setup and hold delays, power consumption analysis, and optimization techniques. The session also improved their skills in designing, testing, and verifying digital architectures through simulation. Overall, the workshop provided a strong foundation in digital hardware design, fostering technical expertise and problem-solving abilities among the students.
